DS1220Y 16k nonvolatile sram DS1220Y 021998 1/8 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? directly replaces 2k x 8 volatile static ram or eeprom ? unlimited write cycles ? lowpower cmos ? jedec standard 24pin dip package ? read and write access times as fast as 100 ns ? full 10% operating range ? optional industrial temperature range of 40 c to +85 c, designated ind pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a8 a9 a10 dq7 dq6 dq5 dq4 dq3 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd ce oe we v cc 24pin encapsulated package 720 mil extended pin description a0a10 address inputs dq0dq7 data in/data out ce chip enable we write enable oe output enable v cc power (+5v) gnd ground description the DS1220Y 16k nonvolatile sram is a 16,384bit, fully static, nonvolatile ram organized as 2048 words by 8 bits. each nv sram has a selfcontained lithium energy source and control circuitry which constantly monitors v cc for an outoftolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is uncon- ditionally enabled to prevent data corruption. the nv sram can be used in place of existing 2k x 8 srams directly conforming to the popular bytewide 24pin dip standard. the DS1220Y also matches the pinout of the 2716 eprom or the 2816 eeprom, allowing direct substitution while enhancing performance. there is no limit on the number of write cycles that can be executed and no additional support circuitry is required for micro- processor interfacing.
DS1220Y 021998 2/8 read mode the DS1220Y executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 11 address inputs (a0a10) defines which of the 2048 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the DS1220Y executes a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initi- ated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. how- ever, if the output drivers are enabled (ce and oe ac- tive) then we will disable the outputs in t odw from its falling edge. data retention mode the DS1220Y provides full functional capability for v cc greater than 4.5 volts and write protects at 4.25 nominal. data is maintained in the absence of v cc without any additional support circuitry. the DS1220Y constantly monitors v cc . should the supply voltage decay, the nv sram automatically write protects itself, all inputs be- come adon't care,o and all outputs become high imped- ance. as v cc falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to ram to retain data. during powerup, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and dis- connects the lithium energy source. normal ram oper- ation can resume after v cc exceeds 4.5 volts.
DS1220Y 021998 3/8 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c; 40 c to +85 c for ind parts storage temperature 40 c to +70 c; 40 c to +85 c for ind parts soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes power supply voltage v cc 4.5 5.0 5.5 v input logic 1 v ih 2.2 v cc v input logic 0 v il 0.0 +0.8 v dc electrical characteristics (t a : see note 10; v cc = 5v 10%) parameter symbol min typ max units notes input leakage current i il 1.0 +1.0 m a i/o leakage current ce > v ih < v cc i io 1.0 +1.0 m a output current @ 2.4v i oh 1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 3.0 7.0 ma standby current ce = v cc 0.5v i ccs2 2.0 4.0 ma operating current t cyc =200 ns (commercial) i cco1 75 ma operating current t cyc =200 ns (industrial) i cco1 85 ma write protection voltage v tp 4.25 v capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 12 pf
DS1220Y 021998 4/8 ac electrical characteristics (t a : see note 10; v cc =5.0v 10%) parameter sym DS1220Y-100 DS1220Y-120 DS1220Y-150 DS1220Y-200 units note parameter sym min max min max min max min max units note read cycle time t rc 100 120 150 200 ns access time t acc 100 120 150 200 ns oe to output valid t oe 50 60 70 100 ns ce to output valid t co 100 120 150 200 ns oe or ce to output active t coe 5 5 5 5 ns 5 output high z from deselection t od 35 35 35 35 ns 5 output hold from address change t oh 5 5 5 5 ns write cycle time t wc 100 120 150 200 ns write pulse width t wp 75 90 100 150 ns 3 address setup time t aw 0 0 0 0 ns write recovery time t wr1 t wr2 0 10 0 10 0 10 0 10 ns ns 12 13 output high z from we t odw 35 35 35 35 ns 5 output active from we t oew 5 5 5 5 ns 5 data setup time t ds 40 50 60 80 ns 4 data hold time t dh1 t dh2 0 10 0 10 0 10 0 10 ns ns 12 13
addresses ce we d out d in t wc t wp v ih v il v ih v il v ih v il v il v il v ih v ih v il v il v il v ih t coe t odw t ds t dh2 data in stable v ih v il v ih v il write cycle 2 t wr2 t aw see notes 2, 3, 4, 6, 7, 8 and 13 DS1220Y 021998 5/8 addresses t rc ce oe d out v ih v il v ih v il v ih v il t acc v ih v ih t co t oe t od t od t oh v il v il v ih t coe t coe v ih output data valid v ol v oh v ol v oh read cycle see note 1 addresses ce we d out d in t wc v ih v il v ih v il v ih v il v il v il v il v il t wp t wr1 t aw v ih v ih t odw t oew high inpedance t ds t dh1 data in stable v ih v il v ih v il write cycle 1 see notes 2, 3, 4, 6, 7, 8 and 12
DS1220Y 021998 6/8 powerdown/powerup condition data retention time t dr t f t pd we , ce v cc leakage current i l supplied from lithium cell t r t rec v tp 3.2v see note 11 powerdown/powerup timing parameter symbol min max units notes ce at v ih before powerdown t pd 0 m s 11 v cc slew from v tp to 0v t f 100 m s v cc slew from 0v to v tp t r 0 m s ce at v ih after powerup t rec 2 ms (t a = 25 c) parameter symbol min max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during a write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period.
DS1220Y 021998 7/8 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. each DS1220Y is marked with a 4digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined as starting at the date of manufacture. 10. all ac and dc electrical characteristics are valid over the full operating temperature range. for commercial prod- ucts, this range is 0 cto 70 c. for industrial products (ind), this range is 40 c to +85 c. 11. in a power down condition the voltage on any pin may not exceed the voltage of v cc . 12. t wr1 , t dh1 are measured from we going high. 13. t wr2 , t dh2 are measured from ce going high. 14. DS1220Y modules are recognized by underwriters laboratory (u.l. ? ) under file e99151 (r). dc test conditions outputs open. all voltages are referenced to ground. ac test conditions output load: 100pf + 1ttl gate input pulse levels: 03.0v timing measurement reference levels input:1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information ds1220 ttp sss iii operating temperature range blank: 0 cto 70 c ind: 40 c to +85 c access 100: 120: 150: 200: speed 100 ns 120 ns 150 ns 200 ns package type blank: 24pin 600 mil dip v cc tolerance y: 10%
DS1220Y 021998 8/8 DS1220Y nonvolatile sram, 24pin 720 mil extended module 24pin pkg dim min max in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.320 33.53 1.340 34.04 0.695 17.65 0.720 18.29 0.390 9.91 0.415 10.54 0.100 2.54 0.130 3.30 0.017 0.43 0.030 0.76 0.120 3.05 0.160 4.06 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.008 0.20 0.012 0.30 0.015 0.38 0.021 0.53 a a 24 114 15 c e f k d g b h j 11 equal spaces at .100 .010 tna
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